Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles

Ieee VLSI projects 2017 | 2017 VLSI project titles

Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles

SL.NO	DOMAIN	PROJECT TITLES	DOWNLOAD	DOWNLOAD	DOWNLOAD
IXV1	MEMORY	Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation	ABSTRACT	BASEPAPER	VIDEO
IXV2	DIGITAL	A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS	ABSTRACT	BASEPAPER	VIDEO
IXV3	DIGITAL	Hybrid LUT/Multiplexer FPGA Logic Architectures	ABSTRACT	BASEPAPER	VIDEO
IXV4	LOWPOWER	A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational and Sequential Circuits	ABSTRACT	BASEPAPER	VIDEO
IXV5	LOWPOWER	Low-Power Variation-Tolerant Nonvolatile Lookup Table Design	ABSTRACT	BASEPAPER	VIDEO
IXV6	LOWPOWER	Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM	ABSTRACT	BASEPAPER	VIDEO
IXV7	DIGITAL	Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators	ABSTRACT	BASEPAPER	VIDEO
IXV8	DELAYLESS	High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator	ABSTRACT	BASEPAPER	VIDEO
IXV9	DELAYLESS	A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO	ABSTRACT	BASEPAPER	VIDEO
IXV10	AREA BASED	A High Throughput List Decoder Architecture for Polar Codes	ABSTRACT	BASEPAPER	VIDEO
IXV11	DSP	Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors	ABSTRACT	BASEPAPER	VIDEO
IXV12	DSP	Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device	ABSTRACT	BASEPAPER	VIDEO
IXV13	DSP	Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks	ABSTRACT	BASEPAPER	VIDEO
IXV14	DELAYLESS	A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications	ABSTRACT	BASEPAPER	VIDEO
IXV15	ANALOG	A Cellular Network Architecture With Polynomial Weight Functions	ABSTRACT	BASEPAPER	VIDEO
IXV16	DSP	Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic	ABSTRACT	BASEPAPER	VIDEO
IXV17	ANALOG	Graph-Based Transistor Network Generation Method for Super gate Design	ABSTRACT	BASEPAPER	VIDEO
IXV18	DELAYLESS	Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication	ABSTRACT	BASEPAPER	VIDEO
IXV19	DSP	LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter	ABSTRACT	BASEPAPER	VIDEO
IXV20	ARITHMATIC	High-Performance NB-LDPC Decoder With Reduction of Message Exchange	ABSTRACT	BASEPAPER	VIDEO
IXV21	ARITHMATIC	High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2^m)	ABSTRACT	BASEPAPER	VIDEO
IXV22	LOWPOWER	Implementing Minimum-Energy-Point Systems with Adaptive Logic	ABSTRACT	BASEPAPER	VIDEO
IXV23	DIGITAL	A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory	ABSTRACT	BASEPAPER	VIDEO
IXV24	AREA BASED	Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers	ABSTRACT	BASEPAPER	VIDEO
IXV25	DIGITAL	One-Cycle Correction of Timing Errors in Pipelines with Standard Clocked Elements	ABSTRACT	BASEPAPER	VIDEO
IXV26	DSP	Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications with Convolution Codes	ABSTRACT	BASEPAPER	VIDEO
IXV27	ARITHMATIC	A Mixed-Decimation MDF Architecture for Radix-2^K Parallel FFT	ABSTRACT	BASEPAPER	VIDEO
IXV28	DELAYLESS	Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order	ABSTRACT	BASEPAPER	VIDEO
IXV29	AREA BASED	A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding	ABSTRACT	BASEPAPER	VIDEO
IXV30	ARITHMATIC	Code Compression for Embedded Systems Using Separated Dictionaries	ABSTRACT	BASEPAPER	VIDEO
IXV31	ANALOG	A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling	ABSTRACT	BASEPAPER	VIDEO
IXV32	DELAYLESS	High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels	ABSTRACT	BASEPAPER	VIDEO
IXV33	DELAYLESS	A High-Speed FPGA Implementation of an RSD-Based ECC Processor	ABSTRACT	BASEPAPER	VIDEO
IXV34	LOWPOWER	Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units	ABSTRACT	BASEPAPER	VIDEO
IXV35	LOWPOWER	Low-Power FPGA Design Using Memoization-Based Approximate Computing	ABSTRACT	BASEPAPER	VIDEO
IXV36	AREA BASED	A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography	ABSTRACT	BASEPAPER	VIDEO
IXV37	LOWPOWER	Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia	ABSTRACT	BASEPAPER	VIDEO
IXV38	DIGITAL	RF Power Gating: A Low-Power Technique for Adaptive Radios	ABSTRACT	BASEPAPER	VIDEO
IXV39	DIGITAL	A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply	ABSTRACT	BASEPAPER	VIDEO
IXV40	DSP	Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application	ABSTRACT	BASEPAPER	VIDEO
IXV41	DSP	Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding	ABSTRACT	BASEPAPER	VIDEO
IXV42	DSP	A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing	ABSTRACT	BASEPAPER	VIDEO
IXV43	ARITHMATIC	A New Binary-Halved Clustering Method and ERT Processor for ASSR System	ABSTRACT	BASEPAPER	VIDEO
IXV44	DSP	The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems	ABSTRACT	BASEPAPER	VIDEO
IXV45	LOWPOWER	Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals	ABSTRACT	BASEPAPER	VIDEO
IXV46	ARITHMATIC	Source Code Error Detection in High-Level Synthesis Functional Verification	ABSTRACT	BASEPAPER	VIDEO
IXV47	NETWORK	In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers	ABSTRACT	BASEPAPER	VIDEO
IXV48	DIGITAL	OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application	ABSTRACT	BASEPAPER	VIDEO
IXV49	MEMORY	A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell	ABSTRACT	BASEPAPER	VIDEO

Ieee VLSI projects 2017 | 2017 VLSI project titles

Ieee VLSI projects 2017

Ieee VLSI projects 2017 | 2017 VLSI project titles

Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 Ieee VLSI projects 2017 Ieee VLSI projects 2017 Ieee VLSI projects 2017 Ieee VLSI projects 2017 Ieee VLSI projects 2017

Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles

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Ieee VLSI projects 2017 | 2017 VLSI project titles

Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles

Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

Hybrid LUT/Multiplexer FPGA Logic Architectures

A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational and Sequential Circuits

Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

A High Throughput List Decoder Architecture for Polar Codes

Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors

Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

A Cellular Network Architecture With Polynomial Weight Functions

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

Graph-Based Transistor Network Generation Method for Super gate Design

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter

High-Performance NB-LDPC Decoder With Reduction of Message Exchange

High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m)

Implementing Minimum-Energy-Point Systems with Adaptive Logic

A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory

Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers

One-Cycle Correction of Timing Errors in Pipelines with Standard Clocked Elements

Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications with Convolution Codes

A Mixed-Decimation MDF Architecture for Radix-2K Parallel FFT

Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order

A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding

Code Compression for Embedded Systems Using Separated Dictionaries

A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

A High-Speed FPGA Implementation of an RSD-Based ECC Processor

Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units

Low-Power FPGA Design Using Memoization-Based Approximate Computing

A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

RF Power Gating: A Low-Power Technique for Adaptive Radios

A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply

Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application

Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing

A New Binary-Halved Clustering Method and ERT Processor for ASSR System

The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems

Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals

Source Code Error Detection in High-Level Synthesis Functional Verification

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application

A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell

Ieee VLSI projects 2017 | 2017 VLSI project titles

Ieee VLSI projects 2017 | 2017 VLSI project titles

Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles

Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles

Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles

Ieee VLSI projects 2017 | 2017 VLSI project titles Ieee VLSI projects 2017 | 2017 VLSI project titles

High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2^m)

A Mixed-Decimation MDF Architecture for Radix-2^K Parallel FFT