VLSI Projects
Get started with your final year engineering projects with us. We are creators of a unique and innovative project Making platform for engineering students, which helps them to gain the real time experience and get the creative mind as well. We offer highly skilled VLSI and Matlab projects for engineering students. We are committed to providing the best VLSI projects and bridging the gap between academic and practical exposure within the engineering students and making them best engineer’s.
IEEE Projects for VLSI 2023 – 2024 Titles
Explore the latest IEEE VLSI projects and Machine Learning Projects for students and researchers. Our wide range of topics includes design and implementation of digital circuits, low power VLSI, FPGA and ASIC design, VLSI testing and verification, and more. Learn and advance your skills with our comprehensive project descriptions and resources.
S. No | DOMAIN | PROJECT TITLES | ABSTRACT | BASEPAPER | COST | VIDEO |
IXV01 | High Speed | COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV02 | High Speed | Efficient Error Estimation for High-Level Design Space Exploration of Approximate Computing Systems | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV03 | Area Efficient | RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV04 | Low Power | Physical Attack Protection Techniques for IC Chip Level Hardware Security | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV05 | Low Power | VLSI Design of Saturation-Based Image Dehazing Algorithm | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV06 | Memory | Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV07 | High Speed | A Real-Time Object Detection Processor With xnor-Based Variable-Precision Computing Unit | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV08 | High Speed | Energy-Efficient Wide-Range Level Shifter With a Logic Error Detection Circuit | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV09 | Low Power | Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV10 | Low Power | AxPPA: Approximate Parallel Prefix Adders | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV11 | High Speed | Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV12 | High Speed | FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV13 | Low Power | ACBN: Approximate Calculated Batch Normalization for Efficient DNN On-Device Training Processor | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV14 | VLSI Communication | A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV15 | Area Efficient | Approximate Softmax Functions for Energy-Efficient Deep Neural Networks | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV16 | Low Power | A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IX17 | Testing | Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IX18 | Low power | A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV19 | High Speed | A Low-Power PPG Processor for Real-Time Biometric Identification and Heart Rate Estimation | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV20 | VLSI Communication | ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV21 | Machine Learning | Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV22 | Area Efficient | A High-Performance Dual-Context MQ Encoder Architecture Based on Extended Lookup Table | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV23 | Low Power | A Triple Burst Error Correction Based on Region Selection Code | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV24 | Area Efficient | Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV25 | High Speed | A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV26 | Area Efficient | Improvement of Accuracy of Fixed-Width Booth Multipliers Using Data Scaling Technology | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV27 | Low Power | Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV26 | Area Efficient | An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV27 | Low Power | A Fully Integrated FVF LDO With Enhanced Full-Spectrum Power Supply Rejection | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV28 | Low Power | Startup Time and Energy-Reduction Techniques for Crystal Oscillators in the IoT Era | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV29 | Area Efficient | Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV30 | Low power | A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
IXV31 | Area Efficient | An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth | ABSTRACT | BASEPAPER | Rs.4000 | VIDEO |
More Titles will be updated Regularly |
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PREVIOUS YEAR PROJECTS
SL.NO | DOMAIN | PROJECT TITLES | DOWNLOAD | DOWNLOAD | DOWNLOAD |
IXV1 | MEMORY | Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation | ABSTRACT | BASEPAPER | VIDEO |
IXV2 | DIGITAL | A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS | ABSTRACT | BASEPAPER | VIDEO |
IXV3 | DIGITAL | Hybrid LUT/Multiplexer FPGA Logic Architectures | ABSTRACT | BASEPAPER | VIDEO |
IXV4 | LOWPOWER | A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational and Sequential Circuits | ABSTRACT | BASEPAPER | VIDEO |
IXV5 | LOWPOWER | Low-Power Variation-Tolerant Nonvolatile Lookup Table Design | ABSTRACT | BASEPAPER | VIDEO |
IXV6 | LOWPOWER | Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM | ABSTRACT | BASEPAPER | VIDEO |
IXV7 | DIGITAL | Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators | ABSTRACT | BASEPAPER | VIDEO |
IXV8 | DELAYLESS | High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator | ABSTRACT | BASEPAPER | VIDEO |
IXV9 | DELAYLESS | A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO | ABSTRACT | BASEPAPER | VIDEO |
IXV10 | AREA BASED | A High Throughput List Decoder Architecture for Polar Codes | ABSTRACT | BASEPAPER | VIDEO |
IXV11 | DSP | Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors | ABSTRACT | BASEPAPER | VIDEO |
IXV12 | DSP | Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device | ABSTRACT | BASEPAPER | VIDEO |
IXV13 | DSP | Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks | ABSTRACT | BASEPAPER | VIDEO |
IXV14 | DELAYLESS | A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications | ABSTRACT | BASEPAPER | VIDEO |
IXV15 | ANALOG | A Cellular Network Architecture With Polynomial Weight Functions | ABSTRACT | BASEPAPER | VIDEO |
IXV16 | DSP | Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic | ABSTRACT | BASEPAPER | VIDEO |
IXV17 | ANALOG | Graph-Based Transistor Network Generation Method for Super gate Design | ABSTRACT | BASEPAPER | VIDEO |
IXV18 | DELAYLESS | Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication | ABSTRACT | BASEPAPER | VIDEO |
IXV19 | DSP | LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter | ABSTRACT | BASEPAPER | VIDEO |
IXV20 | ARITHMATIC | High-Performance NB-LDPC Decoder With Reduction of Message Exchange | ABSTRACT | BASEPAPER | VIDEO |
IXV21 | ARITHMATIC | High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m) | ABSTRACT | BASEPAPER | VIDEO |
IXV22 | LOWPOWER | Implementing Minimum-Energy-Point Systems with Adaptive Logic | ABSTRACT | BASEPAPER | VIDEO |
IXV23 | DIGITAL | A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory | ABSTRACT | BASEPAPER | VIDEO |
IXV24 | AREA BASED | Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers | ABSTRACT | BASEPAPER | VIDEO |
IXV25 | DIGITAL | One-Cycle Correction of Timing Errors in Pipelines with Standard Clocked Elements | ABSTRACT | BASEPAPER | VIDEO |
IXV26 | DSP | Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications with Convolution Codes | ABSTRACT | BASEPAPER | VIDEO |
IXV27 | ARITHMATIC | A Mixed-Decimation MDF Architecture for Radix-2K Parallel FFT | ABSTRACT | BASEPAPER | VIDEO |
IXV28 | DELAYLESS | Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order | ABSTRACT | BASEPAPER | VIDEO |
IXV29 | AREA BASED | A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding | ABSTRACT | BASEPAPER | VIDEO |
IXV30 | ARITHMATIC | Code Compression for Embedded Systems Using Separated Dictionaries | ABSTRACT | BASEPAPER | VIDEO |
IXV31 | ANALOG | A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling | ABSTRACT | BASEPAPER | VIDEO |
IXV32 | DELAYLESS | High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels | ABSTRACT | BASEPAPER | VIDEO |
IXV33 | DELAYLESS | A High-Speed FPGA Implementation of an RSD-Based ECC Processor | ABSTRACT | BASEPAPER | VIDEO |
IXV34 | LOWPOWER | Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units | ABSTRACT | BASEPAPER | VIDEO |
IXV35 | LOWPOWER | Low-Power FPGA Design Using Memoization-Based Approximate Computing | ABSTRACT | BASEPAPER | VIDEO |
IXV36 | AREA BASED | A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography | ABSTRACT | BASEPAPER | VIDEO |
IXV37 | LOWPOWER | Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia | ABSTRACT | BASEPAPER | VIDEO |
IXV38 | DIGITAL | RF Power Gating: A Low-Power Technique for Adaptive Radios | ABSTRACT | BASEPAPER | VIDEO |
IXV39 | DIGITAL | A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply | ABSTRACT | BASEPAPER | VIDEO |
IXV40 | DSP | Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application | ABSTRACT | BASEPAPER | VIDEO |
IXV41 | DSP | Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding | ABSTRACT | BASEPAPER | VIDEO |
IXV42 | DSP | A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing | ABSTRACT | BASEPAPER | VIDEO |
IXV43 | ARITHMATIC | A New Binary-Halved Clustering Method and ERT Processor for ASSR System | ABSTRACT | BASEPAPER | VIDEO |
IXV44 | DSP | The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems | ABSTRACT | BASEPAPER | VIDEO |
IXV45 | LOWPOWER | Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals | ABSTRACT | BASEPAPER | VIDEO |
IXV46 | ARITHMATIC | Source Code Error Detection in High-Level Synthesis Functional Verification | ABSTRACT | BASEPAPER | VIDEO |
IXV47 | NETWORK | In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers | ABSTRACT | BASEPAPER | VIDEO |
IXV48 | DIGITAL | OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application | ABSTRACT | BASEPAPER | VIDEO |
IXV49 | MEMORY | A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell | ABSTRACT | BASEPAPER | VIDEO |
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