Low-Power FPGA Design Using Memoization-Based Approximate Computing
Field-programmable gate arrays (FPGAs) are increasingly used as the computing platform for fast and energy efficient execution of recognition, mining, and search applications. Approximate computing is one promising method for achieving energy efficiency. Compared with most prior works on approximate computing, which target approximate processors and arithmetic blocks, this paper presents an approximate computing methodology for FPGA-based design. It studies memoization as a method for approximation on FPGA and analyzes different architectural and design parameters that should be considered. The proposed design flow leverages on high-level synthesis to enable memoization-based micro-architecture generation, thus also facilitating a C-to-register-transfer-level synthesis. When compared with the previous approaches of bit-width truncation and approximate multipliers, memoization-based approximate computation on FPGA achieves a significant dynamic power saving (around 20%) with very small area overhead (< 5%) and better power-to-signal noise ratio values for the studied image processing benchmarks. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
Enhancement of the project:
increase the length of the input data.
APPROXIMATE computing has been proposed as an alternative to exact computing for power reduction in embedded computing systems. It assumes that the applications under investigation can tolerate approximate results, and hence, exact computation becomes unnecessary. Some application examples are data-mining, search, analytics, and media processing (audio and video), which are collectively referred to as the class of recognition, mining, and search (RMS) applications. Approximation can help to reduce the computation efforts, resulting in lower power