A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding


The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multistandard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting factor in the future. This brief presents the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising the decoding performances. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.