by admin | Jul 2, 2016 | vlsi 2016
High-Performance NB-LDPC Decoder With Reduction of Message Exchange Abstract: This paper presents a novel algorithm based on trellis min–max for decoding non-binary low-density parity check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between...
by admin | Jul 2, 2016 | vlsi 2016
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter Abstract: In this paper, we analyze the contents of lookup tables (LUTs) of distributed arithmetic (DA)-based block least mean square (BLMS) adaptive filter (ADF) and based on...
by admin | Jul 2, 2016 | vlsi 2016
Graph-Based Transistor Network Generation Method for Supergate Design Abstract: Transistor network optimization represents an effective way of improving VLSI circuits. In VLSI digital design, the signal delay propagation, power dissipation, and area of circuits are...
by admin | Jul 2, 2016 | vlsi 2016
Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Abstract: Hardware acceleration has been proved an extremelypromising implementation strategy for the digital signal processing (DSP)domain. Rather than adopting a monolithic application-specific...
by admin | Jul 2, 2016 | vlsi 2016
A Cellular Network Architecture With Polynomial Weight Functions Abstract: Emulations of cellular nonlinear networks on digital reconfigurable hardware are renowned for an efficient computation of massive data, exceeding the accuracy and flexibility of full-custom...
by admin | Jul 2, 2016 | vlsi 2016
Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks Abstract: Soft errors pose a reliability threat to modern electronic circuits. This makes protection against soft errors a requirement for many applications. Communications and signal...
