LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter


In this paper, we analyze the contents of lookup tables (LUTs) of distributed arithmetic (DA)-based block least mean square (BLMS) adaptive filter (ADF) and based on that we propose intra-iteration LUT sharing to reduce its hardware resources, energy consumption, and iteration period. The proposed LUT optimization scheme offers a saving of 60% LUT content for block size 8 and still higher saving for larger block sizes over the conventional design approach. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.