by admin | Jul 2, 2016 | vlsi 2016
Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device Abstract: A multilevel per cell (MLC) technique significantly improves the storage density, but also poses serious data integrity...
by admin | Jul 2, 2016 | vlsi 2016
Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors Abstract: In many digital signal processing applications, some parts of a word stored in the embedded static random access memories (SRAMs) are more important than...
by admin | Jul 2, 2016 | vlsi 2016
A High Throughput List Decoder Architecture for Polar Codes Abstract: While long polar codes can achieve the capacity of arbitrary binary-input discrete memoryless channels when decoded by a low complexity successive-cancellation (SC) algorithm, the error performance...
by admin | Jul 2, 2016 | vlsi 2016
A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO Abstract: Nowadays, many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore,...
by admin | Jul 2, 2016 | vlsi 2016
Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application Abstract: In this paper, we present a novel channelization architecture, which can simultaneously process two channels of complex input data and provide up...
by admin | Jul 2, 2016 | vlsi 2016
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding Abstract: The field of approximate computing has received significant attention from the research community in the past few years, especially in the context of various signal...
