Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents


Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.