A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply


This paper presents a new power-efficient electrocardiogram acquisition system that uses a fully digital architecture to reduce the power consumption and chip area. The proposed architecture is compatible with digital CMOS technology and is capable of operating with a low supply voltage of 0.5 V. In this architecture, no analog block, e.g., low-noise amplifier (LNA), and filters, and no passive elements, such as ac coupling capacitors, are used. A moving average voltage-to time converter is used, which behaves instead of the LNA and anti-aliasing filter. A digital feedback loop is employed to cancel the impact of the dc offset on the circuit, which eliminates the need for coupling capacitors. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.

Enhancement of the project:

Existing System:

A digital signal processor then processes the digital data for monitoring or diagnosis applications. Biomedical signal acquisition systems typically consist of a low-noise amplifier (LNA), a bandpass filter, an analog sample-and-hold, and an analog-to-digital converter (ADC), as shown in Fig. 1(a). While the architecture shown in Fig. 1(a) is typically used, in some cases chopping technique is used to reduce the impact of the flicker noise, as shown in Fig. 1(b).