High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive- and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-µm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz–3.3 GHz. The frequency multiplier achieves power consumption to a frequency ratio of 2.9µW/MHz. The proposed architecture of this paper area and power consumption analysis using tanner tool.
Enhancement of the project:
Increase the multiplier range of the frequency multiplier.
Fig. 1 shows the structures of the recently published frequency multipliers that perform better than most previous frequency multipliers. The frequency multiplier is composed of a D-flip–flop-based pulse generator, multiplication-ratio control logic, and a push–pull-stage based edge combiner, as shown in Fig. 1(a). Owing to its simple edge-combiner structure, this frequency multiplier is suitable for high-frequency multiplied clock generation with low power and a small area.
Fig. 1(b) shows the structure of another frequency multiplier. This frequency multiplier is composed of multiplication-ratio control logic, an AND-gate-based pulse generator, and a differential cascade voltage switch (SW) logic (DCVSL)-stage-based edge combiner. The frequency multiplier can generate the multiplied differential clocks with a small area penalty.
Fig. 1. Structure of the frequency multipliers (a) and (b)
- Speed is less
The proposed DLL-based clock generator is composed of a DLL core and the proposed frequency multiplier, as shown in Fig. 2. To enhance the lock time, which is an important design parameter in the clock generator, a dual-edge-triggered phase-detector-based DLL core is adopted. Similar to previous frequency multipliers, the proposed frequency multiplier is also composed of a pulse generator, multiplication-ratio control logic, and an edge combiner.
Fig. 2. Structure of the proposed clock generator.
To solve the speed and the reliability issues of previous edge combiners, an HSHR-EC, which consists of a precombining stage, overlap canceller, and push–pull stage, as shown in Fig. 3, is proposed. The two-step edge combiner, precombining, and push–pull stage are used to enhance the maximum multiplied clock frequency. The overlap canceller is used to guarantee the stable operation of the frequency multiplier.
Fig. 3. Structure of the proposed HSHR-EC.
Fig. 4 shows the proposed pulse generator and the multiplication-ratio control logic. These two structures have an optimized design to match the delay between the positive- and negative-edge generation paths of the multiplied clock.
Fig. 4. Structure of the proposed pulse generator and the multiplication-ratio control logic
- Reduce the delay
- Tanner tools