by admin | Jul 2, 2016 | vlsi 2016
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing Abstract: Integral histogram image can accelerate the computing process of feature algorithm in computer vision, but exhibits high computation complexity and inefficient...
by admin | Jul 2, 2016 | vlsi 2016
A New Binary-Halved Clustering Method and ERT Processor for ASSR System Abstract: This paper presents an automatic speech–speaker recognition (ASSR) system implemented in a chip which includes a built-in extraction, recognition, and training (ERT) core. For VLSI...
by admin | Jul 2, 2016 | vlsi 2016
Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals Abstract: In this paper, we present a low-power, efficacious, and scalable system for the detection of symptomatic patterns in biological audio signals. The digital audio recordings of...
by admin | Jul 1, 2016 | vlsi 2016
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell Abstract: A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single-ended with dynamic feedback control 8T...
by admin | Jul 1, 2016 | vlsi 2016
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation Abstract: The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an...
by admin | Jul 1, 2016 | vlsi 2016
A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS Abstract: A duty-cycle correction technique using a novel pulse width modification cell is demonstrated across a frequency range of 100 MHz–3.5 GHz. The technique works at frequencies where...
