Hybrid LUT/Multiplexer FPGA Logic Architectures
Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Technology mapping optimizations that target the proposed architectures are also implemented within ABC. Both accounting for complex logic block and routing area while maintaining mapping depth. For fracturable architectures, the proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.