Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers
In this paper, we design a hardware and energy-efficient stochastic lower–upper decomposition (LUD) scheme for multiple-input multiple-output receivers. By employing stochastic computation, the complex arithmetic operations in LUD can be performed with simple logic gates. With proposed dual partition computation method, the stochastic multiplier and divider exhibit high computation accuracy with relative short length stochastic stream. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.