Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

Abstract:

The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an average-8T SRAM architecture, a full-swing local bitline (BL) that is connected to the gate of the read buffer can be achieved with a boosted wordline (WL) voltage. However, in the case of an average-8T SRAM based on an advanced technology, such as a 22-nm FinFET technology, where the variation in threshold voltage is large, the boosted WL voltage cannot be used, because it degrades the read stability of the SRAM. Thus, a full-swing local BL cannot be achieved, and the gate of the read buffer cannot be driven by the full supply voltage (VDD), resulting in a considerably large read delay. To overcome the above disadvantage, in this paper, a differential SRAM architecture with a full-swing local BL is proposed. In the proposed SRAM architecture, full swing of the local BL is ensured by the use of cross-coupled pMOSs, and the gate of the read buffer is driven by a full VDD, without the need for the boosted WL voltage. Various configurations of the proposed SRAM architecture, which stores multiple bits, are analyzed in terms of the minimum operating voltage and area per bit. The proposed SRAM that stores four bits in one block can achieve a minimum voltage of 0.42 V and a read delay that is 62.6 times lesser than that of the average-8T SRAM based on the 22-nm FinFET technology. The proposed architecture of this paper area and power consumption analysis using HSpice.

Enhancement of the project:

Increase the bits size of the SRAM.

Existing System:

Several SRAM cell alternatives with a decoupled read port have been proposed for a low-voltage operation. The advantage of adding a decoupled read port is that it eliminates the tradeoff between the read stability and the write ability in the SRAM array to which the bit-interleaving is not applied; thus, the read stability and write ability can be optimized separately, facilitating a low-voltage operation. An SRAM cell is also susceptible to soft errors induced by α-particles; to address these errors, it is necessary for the SRAM array to exhibit bit-interleaving. Fig. 1 shows a bit-interleaved SRAM array architecture. In a bit-interleaved SRAM array, the selected cells are the SRAM cells targeted for the read or write operation. The row half-selected cells are the SRAM cells located on the selected row and the unselected column, whereas the column half-selected cells are the SRAM cells located on the unselected row and the selected column. During the write operation, the row half-selected cells are disturbed because of the selection of the wordline (WL) of the row half-selected cells. Thus, the stability of the row half-selected cells should also be considered in the SRAM design.

Fig. 1. Selected, half-selected, and unselected cells in a bit-interleaved SRAM array

In this paper, the drawback of the average-8T SRAM architecture based on an advanced technology is analyzed, and a suitable SRAM architecture that overcomes this drawback is proposed. It should be noted that the proposed differential SRAM architecture can resolve the half-select issue without the need for a write-back scheme, and it exhibits a competitive area; it also exhibits a full-swing local bitline (BL) that enables a considerably smaller read delay than that of average-8T SRAM architecture.

Fig. 2 shows the average-8T SRAM architecture and its operational waveform. A block that stores four bits consists of four pairs of cross-coupled inverters, pass gate transistors (PGL1∼4 and PGR1∼4), block mask transistors (MASK1 and MASK2), write access transistors (WR1 and WR2), and read buffers (RD1∼4). A stacked nMOS structure is used as a read buffer to reduce the read BL (RBL and RBLB) leakage. It is important to note that the block select signal (BLK) and WLs (WL1∼4) are row-based signals, whereas the RBLs and write BLs (WBL and WBLB) are column-based signals.

Fig. 2. (a) Average-8T SRAM architecture and (b) its operational waveform

Disadvantages:

  • High area
  • Operating voltage is high

Proposed System:

The proposed differential SRAM stores multiple bits in one block, as in the case of an average-8T SRAM. Fig. 3 shows the architecture of the proposed SRAM that stores i bits in one block. The minimum operating voltage and area per bit of the proposed SRAM depend on the number of bits in one block.

Fig. 3. Proposed SRAM architecture that stores i bits in one block.

Read Operation

The read operation of the proposed SRAM architecture is described in Fig. 4(a). This operation is performed in two phases.

Fig. 4. (a) Read operation and (b) read operational waveform of proposed SRAM architecture.

Write Operation

The write operation of the proposed SRAM architecture is shown in Fig. 5. As shown in this figure, BLK of the selected block is forced to remain at 0 V, and the selected WL is enabled. Further, the WWL is forced to remain at VDD so that the write access transistors are turned ON, and the WBLs are forced to remain at a certain voltage level on the basis of the write data.

Fig. 5. Selected blocks of proposed SRAM architecture during write operation.

Advantages:

  • not require a write-back scheme for bit-interleaving
  • exhibits a competitive area

Software implementation:

  • HSpice

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