Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology


This paper describes a design methodology for CMOS silicon photonic interconnect ICs according to CMOS technology scaling. As the CMOS process is scaled, the endurable voltage stress and the intrinsic gain of the CMOS devices are reduced; therefore, a design of the high swing transmitter and high-gain receiver required at the silicon photonic interface becomes much more challenging. In this paper, a triple-stacked Mach–Zehnder modulator driver and an inverter-based trans-impedance amplifier with inductive feedback are proposed, and the robustness of the proposed designs is verified through Monte Carlo analyses. The prototype ICs are fabricated using a 65-nm CMOS technology. The transmitter exhibits a 6 Vpp output swing, 98-mW power consumption, and 0.04-mm2 active area at 10 Gb/s. The receiver was verified with a commercial photo detector, and it exhibits a 78-dB gain, 25.3-mW power consumption, and 0.18-mm2 active area at 20 Gb/s. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.

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