A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits

Abstract:

Advanced computing systems embed spintronic devices to improve the leakage performance of conventional CMOS systems. High speed, low power, and infinite endurance are important properties of magnetic tunnel junction (MTJ), a spintronic device, which assures its use in memories and logic circuits. This paper presents a PentaMTJ-based logic gate, which provides easy cascading, self-referencing, less voltage headroom problem in precharge sense amplifier and low area overhead contrary to existing MTJ-based gates. PentaMTJ is used here because it provides guaranteed disturbance free reading and increased tolerance to process variations along with compatibility with CMOS process. The logic gate is validated by simulation at the 45-nm technology node using a Verilog A model of the PentaMTJ. The proposed architecture of this paper area and power consumption analysis using HSpice.

Enhancement of the project:

To use the PentaMTJ for various logical circuits:

Existing System:

SPINTRONICS has been under extensive research because of nonvolatility, infinite endurance, and low power. The spin is employed for storing information and the charge for its processing. It has the potential to replace CMOS logic and memory. In deep submicrometer, scaling of CMOS causes the leakage power to dominate over all other power components. Digital signals are represented in conventional CMOS logic by the presence or absence of electrical charge in terms of voltage VDD or ground. However, in Spintronics, digital signals are represented by up and down spin of electron. In recent years, researchers have developed spintronic devices, such as magnetic tunnel junctions (MTJs), which operates on the principle of tunnel magneto resistance (TMR). An MTJ is composed of two ferromagnetic layers separated by an oxide layer with the capability to improve the performance of CMOS logic circuit in terms of power dissipation, area required, and interconnection delay. It can also be easily fabricated using 3-D backend integration process, which is compatible with CMOS process, without any area overhead.

Disadvantages:

  • Extra hardware is needed for complementary outputs
  • Initialize the state of the output MTJ for sensing

 

 

Proposed System:

PentaMTJ

Fig. 1 shows the structure of the PentaMTJ which comprises of two pinned layers: 1) top pinned layer (TPL) and 2) bottom pinned layer (BPL). The magnetization of two pinned layers is in opposite direction and is fixed. In this paper, 1 state is assigned when TPL (pinned 1) is parallel to the free layer and 0 states when BPL (pinned 2) is parallel to the free layer. The proposed structure of PentaMTJ needs less current for writing as compared with the conventional MTJ. It requires current only for converting anti-parallel to parallel state for one stack, the other stack automatically comes into anti-parallel state. Moreover, PentaMTJ provides guaranteed disturbance free reading and increases the tolerance to process variation as per the only reference available in the literature on PentaMTJ.

Fig. 1. Structure of PentaMTJ with two pinned layers (TPL and BPL) and one free layer.

LOGIC GATES USING PENTAMTJ

Logic gates act as basic building blocks for both combinational and sequential circuits. Fig. 2 shows the PentaMTJ-based XOR/XNOR logic gates. For different logic gates, different writing circuitry is required but the sensing portion remains identical.

Fig. 2. XOR/XNOR gates using PentaMTJ.

3-bit GRAY COUNTER

Sequential logic circuits differ from combinational logic circuits as the output of a sequential logic circuit depends upon both the previous output (present state) and the present input. A 3-bit Gray counter is a sequential circuit whose successive states differ in only one digit [12]. The present state in a sequential circuit like Gray counter is stored in flip-flops, which is very power consuming under standby condition. Use of MTJ/PentaMTJ in a sequential circuit is beneficial because in case of unintentional shutdown, the counter can be restored from its previous state instead of its initial state. The previous state is restored from PentaMTJ within few hundred picoseconds. In the Gray counter, PCSA is used for sensing to generate the next state, PentaMTJ for present state storage and the writing circuitry to assign the next state to the present state.

Fig. 3. Circuit diagram of 3-bit Gray counter using PentaMTJ.

Fig. 3 shows the circuit diagram of a 3-bit Gray counter comprising of three PentaMTJs for storage, three PCSAs for sensing, and a writing circuit according to the characteristic (1). An, Bn, and Cn are the stored outputs (present state) whereas An+1, Bn+1, and Cn+1 signify the next state which is to be stored in a PentaMTJ.

Advantages:

  • no extra hardware is needed for complementary outputs
  • no need to initialize the state of the output MTJ for sensing

Software implementation:

  • Hspice
  • A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits

    A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits

    A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits

    A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits

    A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits

    A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits

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