The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems
This paper presents the VLSI architecture and hardware implementation of a highly efficient Deblocking Filter for High Efficiency Video Coding (HEVC) systems. In order to reduce the number of data accesses and thus to enhance the timing efficiency, novel data structures and memory access schemes for image pixels are proposed. Furthermore, a novel edge-fetching order is presented to strike a balance between the processing throughput and complexity. Based on the proposed structure and access pattern, a six-stage pipelined, two-line Deblocking Filter engine with low-latency data access sequence is designed, aiming to achieve high processing throughput while at the same time maintaining low complexity. The detailed storage structure and data access scheme are illustrated and VLSI architecture for the Deblocking Filter engine is depicted in this paper. In addition, the proposed Deblocking Filter is implemented using TSMC 90nm standard cell library. Experimental results based on post-layout estimations show that the proposed design can achieve 60 frames per second for frame resolution of 4096×2048 pixels (Ultra HD resolution) assuming an operating frequency of 100MHz. Moreover, this design occupies area complexity of 466.5 kGE with power consumption of 26.26 mW. In comparison with prior arts targeting on similar system specification and throughput, the proposed design results in a significantly reduced area complexity.The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.