VLSI PROJECTS 2016

1. Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line.
2. A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler
3. Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid   SRAM/MRAM L2 Cache
4. A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS5. A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme6. A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio   Frequency and Microwave Integrated Circuits

7. A Low Complexity-High Throughput QC-LDPC Encoder

8. A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures

9. A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain

10. A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture

11. A Synergetic Use of Bloom Filters for Error Detection and Correction

12. Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC

13. Parallel and Pipelined Architectures for Cyclic Convolution by Block Circulant Formulation Using Low-Complexity Short-Length Algorithms

14. An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS

15. An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability

16. Analysis and Characterization of Capacitance Variation Using Capacitance Measurement Array

17. Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit

18. Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter

19. Compensating Modeling Overlay Errors Using the Weighted Least-Squares Estimation

20. Compensating Modeling Overlay Errors Using the Weighted Least-Squares Estimation

21. Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane

22. Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging

23. Design Techniques to Improve Blocker Tolerance of Continuous-Time __ ADCs

24. Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor

25. Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three

26. Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects

27. Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems

28. Energy-Efficient Soft-Input Soft-Output Signal Detector for Iterative MIMO Receivers

29. Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories

30. Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs

31. Fast Design Optimization Through Simple Kriging Metamodeling: A Sense Amplifier Case Study

32. Fast Radix-10 Multiplication Using Redundant BCD Codes

33. Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint

34. Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n}

35. Fault Tolerant Parallel Filters Based on Error Correction Codes

36. Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis

37. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications

38. Functional Constraint Extraction From Register Transfer Level for ATPG

39. Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems

40. Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs

41. Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution

42. Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding

43. Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding

44. Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection

45. Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes

46. Novel Structures for Cyclic Convolution Using Improved First-Order Moment Algorithm

47. Parallel Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms

48. Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

49. Protein Alignment Systolic Array Throughput Optimization

50. Quaternary Logic Lookup Table in Standard CMOS

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