by admin | Jul 1, 2016 | vlsi 2016
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell Abstract: A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single-ended with dynamic feedback control 8T...
by admin | Jul 1, 2016 | vlsi 2016
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation Abstract: The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an...
by admin | Jul 1, 2016 | vlsi 2016
A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS Abstract: A duty-cycle correction technique using a novel pulse width modification cell is demonstrated across a frequency range of 100 MHz–3.5 GHz. The technique works at frequencies where...
by admin | Jul 1, 2016 | vlsi 2016
A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits Abstract: Advanced computing systems embed spintronic devices to improve the leakage performance of conventional CMOS systems. High speed, low power, and infinite endurance are...
by admin | Jul 1, 2016 | vlsi 2016
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design Abstract: Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high...
