by admin | Jul 2, 2016 | vlsi 2016
Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application Abstract: In this paper, we present a novel channelization architecture, which can simultaneously process two channels of complex input data and provide up...
by admin | Jul 2, 2016 | vlsi 2016
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding Abstract: The field of approximate computing has received significant attention from the research community in the past few years, especially in the context of various signal...
by admin | Jul 2, 2016 | vlsi 2016
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing Abstract: Integral histogram image can accelerate the computing process of feature algorithm in computer vision, but exhibits high computation complexity and inefficient...
by admin | Jul 2, 2016 | vlsi 2016
A New Binary-Halved Clustering Method and ERT Processor for ASSR System Abstract: This paper presents an automatic speech–speaker recognition (ASSR) system implemented in a chip which includes a built-in extraction, recognition, and training (ERT) core. For VLSI...
by admin | Jul 2, 2016 | Ieee 2016
The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems Abstract: This paper presents the VLSI architecture and hardware implementation of a highly efficient Deblocking Filter for High Efficiency Video Coding (HEVC) systems. In order to reduce...
