by admin | Jul 2, 2016 | vlsi 2016
One-Cycle Correction of Timing Errors in Pipelines with Standard Clocked Elements Abstract: One of the most aggressive uses of dynamic voltage scaling is timing speculation, which in turn requires fast correction of timing errors. The fastest existing error correction...
by admin | Jul 2, 2016 | vlsi 2016
A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory Abstract: Although Latin square is a well-known algorithm to construct low-density parity-check (LDPC) codes for satisfying long code length, high code-rate, good correcting...
by admin | Jul 2, 2016 | vlsi 2016
Implementing Minimum-Energy-Point Systems with Adaptive Logic Abstract: Timing-error-detection (TED)-based systems have been shown to reduce power consumption or increase yield due to reduced margins. This paper shows that the increased adaptability can be a great...
by admin | Jul 2, 2016 | vlsi 2016
High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m) Abstract: This paper proposes an efficient pipelined architecture of elliptic curve scalar multiplication (ECSM) over GF(2m). The architecture uses a bit-parallel finite field...
by admin | Jul 2, 2016 | vlsi 2016
High-Performance NB-LDPC Decoder With Reduction of Message Exchange Abstract: This paper presents a novel algorithm based on trellis min–max for decoding non-binary low-density parity check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between...
