by admin | Jul 2, 2016 | Ieee 2016
Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications with Convolution Codes Abstract: This paper presents an algorithm and a VLSI architecture of a configurable joint detection and decoding (CJDD) scheme for...
by admin | Jul 2, 2016 | vlsi 2016
A Mixed-Decimation MDF Architecture for Radix-2K Parallel FFT Abstract: This paper presents a mixed-decimation multipath delay feedback (M 2 DF) approach for the radix-2k fast Fourier transform. We employ the principle of folding transformation to derive the proposed...
by admin | Jul 2, 2016 | vlsi 2016
Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers Abstract: In this paper, we design a hardware and energy-efficient stochastic lower–upper decomposition (LUD) scheme for multiple-input multiple-output receivers. By employing...
by admin | Jul 2, 2016 | vlsi 2016
Hybrid LUT/Multiplexer FPGA Logic Architectures Abstract: Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area...
by admin | Jul 2, 2016 | vlsi 2016
One-Cycle Correction of Timing Errors in Pipelines with Standard Clocked Elements Abstract: One of the most aggressive uses of dynamic voltage scaling is timing speculation, which in turn requires fast correction of timing errors. The fastest existing error correction...
