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Time-Encoded Values for Highly Efficient Stochastic Circuits

by admin | Oct 13, 2017 | Ieee 2016

Stochastic computing (SC) is a promising technique for applications that require low area overhead and fault tolerance, but can tolerate relatively high latency. In the SC paradigm, logical computation is performed on randomized bit streams. In prior work, streams...

Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations

by admin | Oct 13, 2017 | Ieee 2016

Soft errors in combinational logic circuits are emerging as a significant reliability concern for nano scale VLSI designs. This paper presents a novel sensitivity-based gate sizing methodology to reduce the soft error rate (SER) of combinational circuits in the...

Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers

by admin | Sep 16, 2017 | Ieee 2016

In this paper, we propose four 4:2 compressors, which have the flexibility of switching between the exact and approximate operating modes. In the approximate mode, these dual-quality compressors provide higher speeds and lower power consumptions at the cost of lower...

Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication

by admin | Sep 16, 2017 | Ieee 2016

The presence of different noise sources and continuous increase in crosstalk in the deep sub micrometer technology raised concerns for on-chip communication reliability, leading to the incorporation of crosstalk avoidance techniques in error control coding schemes....

Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication

by admin | Sep 16, 2017 | Ieee 2016

Decimal X×Y multiplication is a complex operation, where intermediate partial products (IPPs) are commonly selected from a set of precomputed radix-10Xmultiples. Some works require only[0,5]×X via recoding digits of Y to one-hot representation of signed digits...
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