One-Cycle Correction of Timing Errors in Pipelines with Standard Clocked Elements
One of the most aggressive uses of dynamic voltage scaling is timing speculation, which in turn requires fast correction of timing errors. The fastest existing error correction technique imposes a one-cycle time penalty only, but it is restricted to two-phase transparent latch-based pipelines. We perform one-cycle error correction by gating only the main latch in each stage of the pipeline that precedes a failed stage. This new method is applicable to widely used clocking elements, such as flip-flops and pulsed latches. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.