High-Performance NB-LDPC Decoder With Reduction of Message Exchange

Abstract:

This paper presents a novel algorithm based on trellis min–max for decoding non-binary low-density parity check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node processors, which decreases the storage resources and the wiring congestion and, thus, increases the throughput of the decoder. Our frame error rate performance simulations show that the proposed algorithm has a negligible performance loss for high rate codes with GF(16) and GF(32), and a performance loss smaller than 0.07 dB for high-rate codes over GF(64). The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.

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