Graph-Based Transistor Network Generation Method for Supergate Design
Transistor network optimization represents an effective way of improving VLSI circuits. In VLSI digital design, the signal delay propagation, power dissipation, and area of circuits are strongly related to the number of transistors. This proposed architecture described an efficient graph-based method to generate optimized transistor (switch) networks. The proposed architecture of this paper will be planned to implemented and also analysis the output current, output voltage, area using Dsch31 and micro wind.