Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

Abstract:

Ring oscillators (ROs) are popular due to their small area, modest power, wide tuning range, and ease of scaling with process technology. However, their use in many applications is limited due to poor phase noise and jitter performance. Thermal noise and flicker noise contribute jitter that decreases inversely with oscillation frequency. This paper describes a frequency boost technique to reduce jitter in ROs. We boost the internal oscillation frequency and introduce a frequency divider following the oscillator to maintain the desired output frequency. This approach offers reduced jitter as well as the opportunity to trade off output jitter with power for dynamic performance management. The oscillator has 32 operating modes, corresponding to different values for the ring size and frequency division. In a 0.5-µm CMOS process, the highest oscillation frequency achieved is 25 MHz with a root-mean-square period jitter of 54 ps and a power consumption of 817 µW at 5 V supply. A jitter model for current-starved oscillators was derived and verified by measurement; a direct relationship between oscillation frequency and jitter was derived and measured. Compared with other oscillators, this design achieves the highest performance in terms of jitter per unit interval and figure-of-merit. The performance is expected to improve in more advanced technologies. The results are summarized to offer design guidance based on the frequency boost technique. The proposed architecture of this paper area and power consumption analysis using tanner tool.

Enhancement of the project:

Change the parameter of the architecture.

Existing System:

VOLTAGE-CONTROLLED oscillators (VCOs) are fundamental building blocks for many VLSI systems and are widely used in many timing applications. Current-starved ring oscillators (ROs) are popular as they offer a reasonable balance between area, power, and phase noise, in addition to having the widest tuning range. In comparison with other popular VCO architectures, such as the LC-tank oscillator, the compact design and easy integration of ROs make them attractive, especially in monolithic VLSI systems. Furthermore, these benefits of ROs scale with technology, making them even more attractive in advanced technologies. However, ROs are generally considered to have poor phase noise and jitter performance that adversely affects the system performance. This paper presents a jitter reduction technique to allow more VLSI systems to utilize ROs, which in turn should provide better performance for monolithic systems.

Most of the existing techniques to reduce jitter and phase noise in ROs involve putting an RO in a phase-locked loop (PLL) and relying on the PLL to correct and confine timing and phase error. These techniques focus on minimizing the RO-induced noise in the loop but not on reducing the intrinsic noise. A slew rate balancing circuit equalizes the rising and falling slew rate of the oscillator and, thus, improves the symmetry of the output waveform, so that the up-converted flicker (1/f) noise is minimized.

Disadvantages:

  • Jitter is high

Proposed System:

Jitter in ROs

We briefly summarize Abidi’s model [18] for jitter and phase noise in ROs and introduce the theory underlying the frequency-boost technique. The oscillation frequency fosc in an RO can be estimated as

Where N is the number of inverter stages in the RO, td is the mean delay for one stage, IINV is the controlled current in inverters, VSW is the peak-to-peak swing amplitude in the RO, and Ceff is the effective loading capacitance for each inverter.

Jitter in FDs

When the oscillation frequency is boosted, an FD is required to adjust the RO output to the desired output frequency. However, this frequency division has a negative effect on overall jitter performance. In order to estimate the period jitter, we consider the period uncertainty for two adjacent rising edges in the frequency signal. The effect of frequency division is that instead of two adjacent rising edges, we consider two rising edges that are farther away.

Jitter in RO Plus FD

The effect of total jitter performance of the RO and the FD after division by a factor of A is summarized as

where Fout is the desired output frequency and equals fosc/A. It is clear that the higher the frequency division A (the higher the oscillation frequency fosc), the better the jitter performance.

CIRCUIT DESCRIPTION

The circuit consists of a current-starved VCO, followed by an FD, as shown in Fig. 1. The oscillator structure is a single ended current-starved RO with nine stages of gated current starved inverters (GCSINVs), which can be reconfigured to three, five, and seven stages. The FD has a cascade of seven divide-by-2 (DB2) circuits. The output can be selected from the oscillator or any of the DB2 circuits. The resulting output frequency is the frequency of the oscillator divided by two to the power of the number of DB2 stages, zero to seven.

Fig. 1. System diagram of the current-starved RO (top) and FD (bottom). Switches are introduced as shown to enable reconfigurability. Three sequential inverters on the left sharpen the signal edge of the oscillator to ensure that the DB2 circuit works properly. A resampling DFF is used at the output to minimize the jitter introduced by the FD.

Current-Starved Ring Oscillator

Gated Current-Starved Inverters: The RO consists of nine stages of current-starved inverters. Each inverter has an nMOS switch to ground at the bottom to turn it ON or OFF, as shown in Fig. 2(a). Unused components are disabled to ensure they do not consume power and contribute additional noise to the rest of the circuit.

Bias Generation: In this design, we use a pMOS input transistor for converting control input voltage to current [see Fig. 2(b)]. A source-degeneration resistor is used to increase the linearity of the input voltage to control current. pMOS has the potential to achieve lower frequency sensitivity to power supply voltage compared with nMOS.

Frequency Dividers

The DB2 circuit is a transmission gate-based D-flip- flop (DFF) with its inverted output connected to its D input and using CLK and Q as input and output, respectively.

Control Generator and Switching Circuit

The control generation circuit uses digital logic gates. Control signals are generated based on two controls, N and M. N has two bits and controls the number of stages used in the RO; M has three bits and controls the number of DB2 stages used in the FD.

Advantages:

  • Reduce the jitter
  • increasing FOM

Software implementation:

  • Tanner tools

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

 

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