A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

Abstract:

A duty-cycle correction technique using a novel pulse width modification cell is demonstrated across a frequency range of 100 MHz–3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-µm CMOS technology and occupies an area of 0.011 mm2. It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies. The proposed architecture of this paper area and power consumption analysis using tanner tool.

Enhancement of the project:

Increase the number of correction cycle of the DCC.

Existing System:

In radio frequency (RF) transceivers for modern communication standards, the clocks with a precise 50% duty cycle are necessary. In a receiver, even order harmonics, which arise out of non-50% duty-cycle clocks, result in additional noise folding, and thus degrading the sensitivity. They also cause the second-order nonlinearity and carrier feed-through in some mixer topologies. With the emergence of digitally intensive transmitter architectures, the switching power amplifiers are being used in many cutting-edge applications. The presence of even order harmonics causes performance degradation in terms of linearity, efficiency, and additional out-of-band components. High-speed wireline communication systems also demand very precise clocks. In implementations where a fine phase separation is generated on-chip, non-50% duty-cycle clocks result in direct performance degradation. DRAMs are another application, which require 50% duty-cycle clocks.

Many techniques have been utilized to correct the duty cycle of a clock. Broadly there are two approaches that are followed: 1) analog, with feedback loops and 2) digital, with and without the use of feedback. In one paper, an analog pulsewidth control loop is used with a ring oscillator to generate a reference signal. This is prone to process-variation related errors. In other paper, the analog duty-cycle correction (DCC) uses a current-starving technique to shrink or stretch pulses. An analog loop with a digitally controlled charge pump is presented. Dual analog-loop architecture is used. A non-feedback digital technique using a half cycle delay line is demonstrated, while Kao and Liu describe another non-feedback digital technique. The frequency range over which the correction can be made is limited in the case of non-feedback digital techniques. Digital feedback techniques include the use of a binary search algorithm with SAR, time-to-digital converters, and phase-alignment. Although they have the advantage of faster settling time, they are limited by the speed of the technology. Analog techniques can be exploited where digital techniques fail. In addition, the analog techniques can be less complicated than their digital counterparts.

Disadvantages:

Use limited range of frequency

Proposed System:

Architecture of the duty-cycle corrector

The DCC technique is based on a negative feedback loop, as shown in Fig. 1. The incoming differential waveforms (V + in and V − in) are processed by a pulse width modification cell (PMC), which performs pulse width expansion and contraction.

Fig. 1. Architecture of the duty-cycle corrector.

Pulse width Modification Cell

Fig. 2 shows the actual implementation of the PMC. When the rise or fall times are increased by reducing the drive strength, the pulse width is contracted by the comparator. Conversely, when the rise or fall times are shortened, there is pulse width expansion. The last inverter stage acts as the comparator.

Fig. 2. Schematic of the PMC.

Duty-Cycle Detector

The DCD produces a differential analog output corresponding to the input duty cycle. It is analogous to a charge pump used in most PLLs. In this implementation, the DCD is a DA-based filter. The pole is placed well below the lowest frequency of operation of the loop. The input signals are integrated with the average value of the signal being proportional to the duty cycle.

Complete Schematic

The complete circuit schematic is shown in Fig. 3. Multiple units of the PMC are cascaded. The common mode voltages VCM1 and VCM2 are locally generated on chip.

Fig. 3. Circuit diagram of the full DCC loop showing the cascade of PMCs, DCD, and the DA with the feedback loop completed.

Advantages:

operate over a very wide frequency range
high-speed digital links

Software implementation:

Tanner tools

A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS