Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

Abstract:

Design of a low-energy power-ON reset (POR) circuit is proposed to reduce the energy consumed by the stable supply of the dual supply static random access memory (SRAM), as the other supply is ramping up. The proposed POR circuit, when embedded inside dual supply SRAM, removes its ramp-up constraints related to voltage sequencing and pin states. The circuit consumes negligible energy during ramp-up, does not consume dynamic power during operations, and includes hysteresis to improve noise immunity against voltage fluctuations on the power supply. The POR circuit, designed in the 40-nm CMOS technology within 10.6-µm2 area, enabled 27× reduction in the energy consumed by the SRAM array supply during periphery power-up in typical conditions. The proposed architecture of this paper area and power consumption analysis using tanner tool.

Enhancement of the project:

 

 

Existing System:

With the emergence of multiple functionalities inside a single system on chip (SoC), there is a growing need for power optimization. Advanced SoC consists of multiple dedicated subsystems that are divided into multiple voltage and power domains. Embedded static random access memory (SRAM) often constraints the minimum voltage of a subsystem due to its extremely dense layout and high multiplicity. As a work-around, the SRAM array voltage (VA) is supplied by a dedicated voltage that does not scale with the periphery logic. However, the SRAM periphery voltage (VP) is shared with the digital part of the subsystem. Such a dual supply SRAM enables very low voltage without any overhead associated with managing the SRAM interface. Isolation cells that are inserted at the boundary of power domains are embedded in such dual supply SRAMs. Fig. 1(a) shows such an SRAM with VP, VA, and the isolation signal (ISO).

Similar to the scenario of multiple voltage domain systems, dual rail SRAM poses sequencing constraints on VA and VP, and ISO pin state constraint while VP power up. In the context of multiple voltage domains, meeting such constraints is difficult to implement and verify, making the design error-prone. If the ISO pin constraint is not satisfied, a spurious current glitch occurs from the stable supply VA when VP is powered-up [Fig. 1(d)]. This can cause malfunctioning of the adjacent power domain that shares the array supply. As an example, the general purpose CPU core and the Graphics Processor Unit (GPU) core have independent power supply [VCPU and VGPU, respectively, as shown in Fig. 1(e)], but share the memory array supply (VARRAY). When the GPU is powered-up with SRAM ISO = 0 and the CPU is running, it may cause malfunction of the CPU.

Fig. 1. (a) Dual supply SRAM. (b) Sample power-ON sequence. (c) Embedded isolation strategy. (d) Unwanted glitch in current consumption if ISO = 0 during power-up. (e) CPU and GPU sharing the memory array supply. (f) GPU power-ON sequence when CPU is running.

Disadvantages:

  • Energy consumption is high

Proposed System:

The proposed circuit is described in Fig. 2. The circuit detects the ramp-up of periphery supply VP using the array supply VA. The output signal OUT can be used as the ISO, to ensure that there is no direct path between the VA and the common ground during VP ramp-up. This section describes, in detail, the functionality of the proposed POR circuit.

Basic Functionality: Three Stages

The POR circuit can be split into three stages

  • Sensing stage that determines the input voltage VP at which the signal OUT makes the transition. This stage is similar to an inverter, but the devices have three (or two) times the threshold voltage (VT ) due to the division of the input voltage (VP) using diodes. This extremely high value of effective VT (VT−EFF) is useful in three ways.
    1. Both nMOS (N11–N13) and pMOS (P11–P13) are not switched-ON simultaneously during the VP transition, thereby removing crowbar current in this stage.
    2. It is used to track the ramp-up rate of VP, as the trip point is of similar order as VT −EFF.
    3. It allows the different thresholds of VP detection during ramp-up and ramp-down, thereby enabling hysteresis needed for improved noise immunity against voltage fluctuations during power-up.
  • Sequencing Stage that ensures the correct sequence of the enable signals in the third stage, and consequently zero crowbar current in that stage.
  • Push–Pull Output Stage that amplifies OUT during VP transition and maintains it when VP is stable.

Advantages:

  • reduce the energy consumed during supply ramp-up in a dual supply SRAM

Software implementation:

  • Tanner tools

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM 

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM 

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM 

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

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