by admin | Oct 13, 2017 | Ieee 2016
The need for ultralow-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be...
by admin | Oct 13, 2017 | Ieee 2016
In CMOS-based application-specific integrated circuit (ASIC) designs, total power consumption is dominated by dynamic power, where dynamic power consists of two major components, namely, switching power and internal power. In this paper, we present a low-power design...
by admin | Oct 13, 2017 | Ieee 2016
This paper presents a design approach for improving energy-efficiency and throughput of parallel architectures in near- and sub-threshold voltage circuits. The focus is to suppress leakage energy dissipation of the idle portions of circuits during active modes, which...
by admin | Oct 13, 2017 | Ieee 2016
Today’s multiprocessor platforms employ the network-on-chip (NoC) architecture as the preferable communication backbone. Conventional NoCs are designed predominantly for unicast data exchanges. In such NoCs, the multicast traffic is generally handled by converting...
by admin | Oct 13, 2017 | Ieee 2016
During fail data collection, a tester collects information that is useful for defect diagnosis. If fail data collection can be terminated early, the tester time as well as the volume of fail data will be reduced. Test reordering can enhance the ability to terminate...
by admin | Oct 13, 2017 | Ieee 2016
Although the modern automatic test pattern generation (ATPG) tools can efficiently produce near-optimal test sets with high fault-coverage for a circuit-under-test, a diagnostic test set (DTS), which is needed for fault localization, is much more challenging to...
